Phase locked loops (PLL) are known to be used in a wide variety of electronic equipment. For example, PLLs are used in telecommunication equipment, microprocessors, microcontroller, etc. to provide an output oscillation signal that is locked in phase, i.e., synchronized, with an incoming oscillating signal. By locking the output oscillation signal with the incoming oscillating signal, which may be digital signal representing data or an external clock signal, information can be extracted from the incoming oscillation signal, or an incoming signal, with minimal risk of data loss.
A PLL performs the locking function by receiving the incoming oscillating signal and comparing it with a feedback signal. This comparison is performed by a phase detector which provides a charge up signal when the incoming oscillating signal leads the feedback signal (is operating at a faster frequency) or a charge down signal when the incoming oscillation signal lags the feedback signal (is operating at a slower frequency). A charge pump receives the charge up or charge down signal and produces a control voltage therefrom. In general, the charge pump functions like a capacitor, where the charge up signal increases the voltage across the capacitor and the charge down signal decreases the voltage.
A voltage controlled oscillator (VCO) generates the output oscillation signal in response to the control voltage. The VCO includes an odd number of inverters interoperably coupled to provide a ring oscillation, where each inverter provides a controlled delay. The control signal regulates the delay of each inverter such that the overall delay of the ring oscillator matches, is some multiple of, or is some fraction of the frequency of the incoming oscillation signal. The output oscillation signal is fed back to the phase detector via a feedback divider to produce the feedback signal.
As is known, PLLs are being incorporated on integrated circuits (IC) to help increase the operating rates of many ICs. As the operating rates increase, control of the inverter delays becomes an ever increasing problem. One implementation to more precisely control the inverter delays is disclosed in IEEE Journal of Solid State Circuits, Vol 27, No. 11, November 1992, page 1599, entitled "A PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors", authored by Young, Greason, and Wong. In their paper, Young et al. disclose controlling the inverters of a ring oscillator via a replica inverter stage. The replica inverter is staticly biased to produce a gate control voltage for each of the inverters in the ring oscillator. While this static approach works well in many applications, it is process dependent, thus yielding different responses from different process batches. In addition, this approach becomes unstable at low frequencies.
Therefore, a need exists for a method and apparatus of a controlled oscillator that provides a dynamic gate control signal and is stable at low frequencies.